Institutions | About Us | Help | Gaeilge
rian logo


Mark
Go Back
Design Of High Frequency Digital Phase Locked Loops
Daniels, Brian; Farrell, Ronan
This paper considers the stability of high order Charge Pump Phase Lock Loop (CP-PLL), proposing a novel means of identifying stable regions for such systems. Traditional design techniques are inefficient for high frequency, high order CPPLL systems. This paper proposes an accurate and efficient means of identifying stable regions for 2nd and 3rd order high frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL responses it is shown that the proposed stability technique is a significant improvement over existing linear methods.
Keyword(s): Electronic Engineering; Stability; Charge Pump; Phase Locked Loop; High Frequency.
Publication Date:
2006
Type: Conference item
Peer-Reviewed: Yes
Institution: Maynooth University
Citation(s): Daniels, Brian and Farrell, Ronan (2006) Design Of High Frequency Digital Phase Locked Loops. In: UNSPECIFIED.
Publisher(s): Institution of Engineering and Technology
File Format(s): application/pdf
Related Link(s): http://eprints.maynoothuniversity.ie/601/1/ISSC_bdaniels.pdf
First Indexed: 2014-09-21 05:17:17 Last Updated: 2015-03-23 05:01:38