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Time-Interleaved Sigma-Delta Modulators for FPGAs
Podsiadlik, Tomasz; Farrell, Ronan
This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (ΣΔ) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signalto-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass ΣΔ modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.
Keyword(s): Sampling frequency; sigma-delta; time interleaved (TI)
Publication Date:
Type: Journal article
Peer-Reviewed: Yes
Institution: Maynooth University
Citation(s): Podsiadlik, Tomasz and Farrell, Ronan (2014) Time-Interleaved Sigma-Delta Modulators for FPGAs. IEEE Transactions on Circuits and Systems II: Express Briefs, 61 (10). pp. 808-812. ISSN 1549-7747
Publisher(s): Institute of Electrical and Electronics Engineers
File Format(s): other
Related Link(s):
First Indexed: 2018-12-06 06:00:46 Last Updated: 2018-12-06 06:00:46