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Stress modelling of multi level interconnect schemes for future deep submicron device generations
Gonzales Montes DeOca, Carlos; Foley, Sean; Mathewson, Alan; Rohan, James F.
Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect scheme for integrated circuits for the future because of the low resistance and capacitance that they offer which can improve circuit performance by more than 30% over conventional interconnect schemes. This paper addresses the thermomechanical stresses in the Cu/Low k interconnect scheme through numerical simulation and identifies the locations of maximum stress in the structure with view to providing information on the impact that different dielectric materials have on the stress distribution in the interfaces between metals and dielectric layers.
Keyword(s): Titanium nitride; Copper layer; Finite element modelling simulation Thermomechanical stress; Metal barrier
Publication Date:
2001
Type: Conference item
Peer-Reviewed: Yes
Language(s): English
Institution: University College Cork
Citation(s): Gonzales Montes De Oca , C., Foley, S., Mathewson, A. and Rohan, J. F. (2001) 'Stress Modelling of Multi Level Interconnect Schemes For Future Deep Submicron Device Generations', SISPAD 01: Simulation of Semiconductor Processes and Devices, Athens, Greece, 5-7 September, Vienna: Springer Vienna, pp. 364-367. doi: 10.1007/978-3-7091-6244-6
Publisher(s): Springer
Alternative Title(s): Stress modeling of multi level interconnect schemes for future deep submicron device generations
File Format(s): application/pdf
Related Link(s): https://link.springer.com/chapter/10.1007/978-3-7091-6244-6_83
First Indexed: 2019-04-03 06:30:38 Last Updated: 2019-04-05 06:30:16