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Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
Koskin, Eugene; Galayko, Dimitri; Feely, Orla; Blokhina, Elena
In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.
Keyword(s): Oscillators; Detectors; Frequency control; Clocks; Mathematical model; Phase frequency detector; Phase locked loops; Microprocessor chips; Network topology
Publication Date:
2019
Type: Journal article
Peer-Reviewed: Unknown
Language(s): English
Institution: University College Dublin
Publisher(s): IEEE
First Indexed: 2019-05-11 06:30:56 Last Updated: 2019-05-11 06:30:56