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Efficient hardware architectures for MPEG-4 core profile
Larkin, Daniel; Kinane, Andrew; Muresan, Valentin; O'Connor, Noel E.
Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile algorithms, namely; texture motion estimation (TME), binary motion estimation (BME)and the shape adaptive discrete cosine transform (SA-DCT). The proposed ME designs may also be used for H.264, since both architectures can handle variable block sizes. Both ME architectures employ early termination techniques that reduce latency and save needless memory accesses and power consumption. They also use a pixel subsampling technique to facilitate parallelism, while balancing the computational load. The BME datapath also saves operations by using Run Length Coded (RLC) pixel addressing. The SA-DCT module has a re-configuring multiplier-less serial datapath using adders and multiplexers only to improve area and power. The SA-DCT packing steps are done using a minimal switching addressing scheme with guarded evaluation. All three modules have been synthesised targeting the WildCard-II FPGA benchmarking platform adopted by the MPEG-4 Part9 reference hardware group.
Keyword(s): Digital video
Publication Date:
Type: Other
Peer-Reviewed: Unknown
Language(s): English
Institution: Dublin City University
Citation(s): Larkin, Daniel, Kinane, Andrew, Muresan, Valentin and O'Connor, Noel E. ORCID: 0000-0002-4033-9135 <> (2005) Efficient hardware architectures for MPEG-4 core profile. In: IMVIP 2005 - 9th Irish Machine Vision and Image Processing Conference, 30-31 August 2005, Belfast, Northern Ireland.
Publisher(s): School of Computer Science, Queens University Belfast
File Format(s): application/pdf
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First Indexed: 2009-11-05 02:00:35 Last Updated: 2019-02-09 07:04:14